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Extensão do ASiA para simulação de arquiteturas de computadores.; ASiA extension for computer architecture simulation.

Bruschi, Sarita Mazzini
Fonte: Biblioteca Digitais de Teses e Dissertações da USP Publicador: Biblioteca Digitais de Teses e Dissertações da USP
Tipo: Dissertação de Mestrado Formato: application/pdf
Publicado em 09/10/1997 Português
Relevância na Pesquisa
66.15%
Esta dissertação de Mestrado apresenta uma extensão do ASiA (Ambiente de Simulação Automático), para simulação de arquiteturas de computadores, denominada Módulo Arquitetura. Este módulo possibilita que o usuário utilize arquiteturas já definidas (alterando ou não os seus parâmetros) ou desenvolva o modelo de uma nova arquitetura utilizando ferramentas específicas para simulação de arquitetura de computadores. Dois exemplos ilustram a utilização do Módulo Arquitetura, destacando as vantagens de sua aplicação tanto em ensino como em pesquisa. Este trabalho apresenta ainda algumas alterações efetuadas no ASiA para torná-lo mais amigável e flexível. Uma revisão bibliográfica dos assuntos relacionados ao tema é também apresentada.; This MSc dissertation presents an extension of the ASiA (Ambiente de Simulação Automático) for computer architecture simulation, named Architecture Module. This module allows the use of previously defined architectures (with possible alteration of parameters) or new architecture models using specific tools for computer architecture simulation. Two examples show the utilization of the Architecture Module highlighting its advantages as both a teaching and a research tool. This work also presents some improvements to the ASiA with the aim of becoming more friendly and flexible. A literature review of the subjects related to the general theme is also presented.

Proposta e simulação de uma arquitetura RISC; Design and simulation of a RISC architecture

Valente, Fredy Joao
Fonte: Biblioteca Digitais de Teses e Dissertações da USP Publicador: Biblioteca Digitais de Teses e Dissertações da USP
Tipo: Dissertação de Mestrado Formato: application/pdf
Publicado em 12/04/1991 Português
Relevância na Pesquisa
56.06%
RISC - Uma nova tendência em arquitetura de computadores. Este trabalho apresenta um estudo de como surgiu esta nova arquitetura, e suas características básicas, que a diferencia das arquiteturas convencionais. Uma proposta de microprocessador RISC é apresentada, com sua rota de dados completamente detalhada. Um simulador para arquitetura RISC foi então construído, para se testar este microprocessador. Para validar o simulador, que é a idéia principal deste trabalho, e para se avaliar a arquitetura do microprocessador proposto, usou-se o benchmark Dhrystone, e os resultados foram comparados com máquinas comerciais.; RISC - A new trend in computer architecture. This work presents a study of how this new architecture emerged, and the basic caracteristics that diferentiate it from the conventional architectures. A proposed RISC microprocessor is presented with the completely detailed data-path. A simulator for the RIse architecture was built to test this microprocessor. To validate the simulator, which is the main idea of this work, and to evaluate the architecture of the proposed microprocessor, the Dhrystone benchmark was used and the results were compared with commercial machines.

Expansão da arquitetura de conjunto de instruções MIPS para suporte à robótica; Instruction set architecture expansion of the mips processor for robotics support

Cruz, Vicente Silva
Fonte: Universidade Federal do Rio Grande do Sul Publicador: Universidade Federal do Rio Grande do Sul
Tipo: Trabalho de Conclusão de Curso Formato: application/pdf
Português
Relevância na Pesquisa
56.08%
Arquitetura de computadores é uma área que tem se desenvolvido muito nos últimos anos, e as pesquisas são cada vez mais crescentes. Os avanços tecnológicos atuais nos permitem processar grandes quantidades de dados em pouco tempo, e também auxiliam diversas áreas do conhecimento, como a robótica. Este trabalho tem por objetivo propor a extensão da arquitetura de conjunto de instruções do processador de propósitos gerais MIPS através da inclusão de instruções que auxiliam nos cálculos necessários ao movimento de robôs. Para atingir esse objetivo fez-se um estudo na área da robótica para verificar os tipos de robôs existentes, seguido da análise matemática dos movimentos realizados por esses robôs, e da elaboração das novas instruções. A inclusão das operações robóticas no conjunto de instruções foi feita em duas etapas: a primeira envolveu a modificação e simulação do novo ISA no nível de arquitetura, ou seja, com a abstração dos detalhes físicos de aumento de área e velocidade, e a segunda, o desenvolvimento no nível de hardware para a obtenção desses valores físicos. A primeira etapa teve o objetivo de avaliar o desempenho de velocidade do novo ISA em relação ao original, obtidos através da simulação de uma aplicação que emula o movimento de um braço robótico. Uma vez que se constatou um ganho significativo de desempenho de velocidade com esta inclusão...

PROTEUS, a microprogrammable, multiprocessor computer

Kesselman, Joseph Jay
Fonte: Massachusetts Institute of Technology Publicador: Massachusetts Institute of Technology
Tipo: Tese de Doutorado Formato: 126 leaves; 8510589 bytes; 8510348 bytes; application/pdf; application/pdf
Português
Relevância na Pesquisa
55.85%
by Joseph Jay Kesselman Jr.; Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982.; MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING

VISTA : a visualization tool for computer architects; Visualization tool for computer architects

Mihalik, Aaron D. (Aaron Daniel), 1980-
Fonte: Massachusetts Institute of Technology Publicador: Massachusetts Institute of Technology
Tipo: Tese de Doutorado Formato: 55 leaves; 3599683 bytes; 3605553 bytes; application/pdf; application/pdf
Português
Relevância na Pesquisa
56.2%
As computer architectures continue to grow in complexity, software developers and hardware engineers cope with the increasing complexity by developing proprietary applications, simulations and tool sets to understand the behavior of these complex systems. Although the field of information visualization is leading to powerful applications in many areas, information visualization applications for computer architecture development are either tightly coupled with a specific architecture or target a wide range of computer system data. This thesis introduces the Visualization Tool for Computer Architects (VISTA) Environment. The VISTA Environment is an extensible and modular information visualization environment for hardware engineers, software developers and educators to visualize data from a variety of computer architecture simulations at different levels of abstraction. The VISTA Environment leverages common attributes in simulation data, computer architecture visualizations, and computer architecture development methods to create a powerful information visualization environment to aid in designing, understanding and communicating complex computer architectures.; by Aaron D. Mihalik.; Thesis (M. Eng.)--Massachusetts Institute of Technology...

6.823 Computer System Architecture, Spring 2002; Computer System Architecture

Asanovic, Krste; Arvind, V.; Devadas, Srinivas; Hoe, James C. (James Chu-Yue)
Fonte: MIT - Massachusetts Institute of Technology Publicador: MIT - Massachusetts Institute of Technology
Formato: 15904 bytes; 18116 bytes; 76031 bytes; 38470 bytes; 13521 bytes; 17491 bytes; 17208 bytes; 11 bytes; 4586 bytes; 21366 bytes; 11602 bytes; 38351 bytes; 4755 bytes; 27322 bytes; 25313 bytes; 4039 bytes; 301 bytes; 354 bytes; 339 bytes; 180 bytes; 285 bytes
Português
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Emphasizes the relationship among technology, hardware organization, and programming systems in the evolution of computer architecture. Pipelined, out-of-order, and speculative execution. Superscaler, VLIW, vector, and multithreaded processors. Addressing structures and virtual memory, and exception handling. I/O and memory systems. Parallel computers; message passing and shared memory systems. Memory models, synchronization, and cache coherence protocols. Vector supercomputers. Assumes an undergraduate knowledge of computer systems. From the course home page: Course Description 6.823 is a study of the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems. Topics may include: instruction set design; processor micro-architecture and pipelining; cache and virtual memory organizations; protection and sharing; I/O and interrupts; in-order and out-of-order superscalar architectures; VLIW machines; vector supercomputers; multithreaded architectures; symmetric multiprocessors; and parallel computers.

16 Cards to Get Into Computer Organization

Tabik, Siham; Romero, Luis F.
Fonte: Universidad de Granada. Departamento de Arquitectura y Tecnolog??a de Computadores Publicador: Universidad de Granada. Departamento de Arquitectura y Tecnolog??a de Computadores
Tipo: Artigo de Revista Científica
Português
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This paper presents a novel educative activity for teaching computer architecture fundamentals. This activity is actually a game that uses 16 cards and involves about twenty active participant students. Executing this activity in the fi rst class of the course allows the studentin only 45 minutes to acquire the fundamental concepts of computer organization. The results of the surveys that evaluate the proposed activity together with the grades obtained by the students at the end of course corroborate the importance of the proposed game in the assimilation of more complex concepts in computer architecture.

An approach towards high productivity computing

Shoyat, Zorislav
Fonte: Universidade Carlos III de Madrid Publicador: Universidade Carlos III de Madrid
Tipo: info:eu-repo/semantics/publishedVersion; info:eu-repo/semantics/bookPart; info:eu-repo/semantics/conferenceObject
Publicado em /11/2014 Português
Relevância na Pesquisa
56.03%
The notion of what exactly we mean by productivity is largely depending on the active paradigms of a particular field and, on a global level, on the present prevailing social, cultural, scientific and spiritual paradigms and environment. It follows that in a long term any specific definition of productivity will have to be changed. Unfortunately, due to the historical processes, present day human-computer communication is on an extremely low level of language complexity. Consequently our present day productivity in using computers from the idea till the implementation is very low. This is primarily due to the circulus vitiosus of interdependecy of (hardware) computer architectures and popular computer programming languages based on the designs of the first Electronic Brains of the mid-last century. The natural, human Language is the prime Human tool for building a common model of the Universe, a huge fractal dynamic system, i.e. machine, whose sub-machines are smaller fractal machines consisting of a series which goes through dialects, sociolects down to idiolects. On the other hand, regarding strictly formal non-adaptable "programming" languages we see that almost all our computer linguistic efforts are oriented towards fixed expressions which are simple enough to be easily and efficiently translated into the scalar serial presently prevailing computer architecture(s). Therefore a new...

Chameleon C2HDL Design Tool In Self-Configurable Ultrascale Computer Systems Based On Partially Reconfigurable FPGAs

Melnyk, Anatoliy; Melnyk, Viktor; Tsyhylyk, Lyubomyr
Fonte: Universidade Carlos III de Madrid Publicador: Universidade Carlos III de Madrid
Tipo: info:eu-repo/semantics/publishedVersion; info:eu-repo/semantics/bookPart; info:eu-repo/semantics/conferenceObject
Publicado em /10/2015 Português
Relevância na Pesquisa
55.88%
The FPGA-based accelerators and reconfigurable computer systems based on them require designing the applicationspecific processors soft-cores and are effective for certain classes of problems only, for which these soft-cores were previously developed. In Self-Configurable FPGA-based Computer Systems the challenge of designing the application-specific processors soft-cores is solved with use of the C2HDL tools, allowing them to be generated automatically. In this paper, we study the questions of the self-configurable computer systems efficiency increasing with use of the partially reconfigurable FPGAs and Chameleonc C2HDL design tool, corresponding to the goals of the project entitled "Improvement of heterogeneous systems efficiency using self-configurable FPGA-based computing" which is a part of the NESUS action. One of the features of the Chameleonc C2HDL design tool is its ability to generate a number of application-specific processors soft-cores executing the same algorithm that differ by the amount of FPGA resources required for their implementation. If the self-configurable computer systems are based on partially reconfigurable FPGAs, this feature allows them to acquire in every moment of its operation such a configuration that will provide an optimal use of its reconfigurable logic at a given level of hardware multitasking.; Proceedings of: Second International Workshop on Sustainable Ultrascale Computing Systems (NESUS 2015). Krakow (Poland)...

Software Communications Architecture (SCA) compliant software defined radio design for IEEE 802.16 wirelessman-OFDMtm transceiver

Low, Kian Wai
Fonte: Monterey, California. Naval Postgraduate School Publicador: Monterey, California. Naval Postgraduate School
Tipo: Tese de Doutorado Formato: xxii, 74 p. : col. ill. ;
Português
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Demands for seamless mobile communications are driving the research and development of software defined radio (SDR), which enables a single terminal to transmit and receive in distinct wireless systems through a simple change in software to reconfigure the terminal's functions. Its application areas include military use, home networks, intelligent transport systems and cellular communications. Several SDR software architectures have been developed during the last few years. One implementation of the Software Communications Architecture is the Open Source SCA Implementation

ADAM: A Decentralized Parallel Computer Architecture Featuring Fast Thread and Data Migration and a Uniform Hardware Abstraction

Huang, Andrew "bunnie"
Fonte: MIT - Massachusetts Institute of Technology Publicador: MIT - Massachusetts Institute of Technology
Formato: 299 p.; 13404896 bytes; 2307234 bytes; application/postscript; application/pdf
Português
Relevância na Pesquisa
66.1%
The furious pace of Moore's Law is driving computer architecture into a realm where the the speed of light is the dominant factor in system latencies. The number of clock cycles to span a chip are increasing, while the number of bits that can be accessed within a clock cycle is decreasing. Hence, it is becoming more difficult to hide latency. One alternative solution is to reduce latency by migrating threads and data, but the overhead of existing implementations has previously made migration an unserviceable solution so far. I present an architecture, implementation, and mechanisms that reduces the overhead of migration to the point where migration is a viable supplement to other latency hiding mechanisms, such as multithreading. The architecture is abstract, and presents programmers with a simple, uniform fine-grained multithreaded parallel programming model with implicit memory management. In other words, the spatial nature and implementation details (such as the number of processors) of a parallel machine are entirely hidden from the programmer. Compiler writers are encouraged to devise programming languages for the machine that guide a programmer to express their ideas in terms of objects, since objects exhibit an inherent physical locality of data and code. The machine implementation can then leverage this locality to automatically distribute data and threads across the physical machine by using a set of high performance migration mechanisms. An implementation of this architecture could migrate a null thread in 66 cycles -- over a factor of 1000 improvement over previous work. Performance also scales well; the time required to move a typical thread is only 4 to 5 times that of a null thread. Data migration performance is similar...

The raw router : gigabit routing on a general-purpose microprocessor; raw router : an analysis and evaluation of a parallel routing architecture

Anderson, James William, 1981-
Fonte: Massachusetts Institute of Technology Publicador: Massachusetts Institute of Technology
Tipo: Tese de Doutorado Formato: 60 p.; 2291026 bytes; 2290832 bytes; application/pdf; application/pdf
Português
Relevância na Pesquisa
56.04%
Conventionally, high-speed routers are built using custom hardware, typically dubbed as network processors. A prominent example of such a network processor is the Intel IXP1200. Such a network processor typically takes years of effort in the design, fabrication and refinement of the custom hardware, and, worst, must be frequently redesigned to meet the oft-changing requirements of emerging network applications. This thesis presents the design and implementation of a software gigabit network router on a general-purpose microprocessor using MIT's Raw microprocessor. The Raw processor, developed by the Computer Architecture Group at MIT, has sixteen RISC processors, arranged as a grid, that communicate through programmable switches and hardware network interconnects with single-cycle latencies. As opposed to previous high-speed network routers, the Raw router is built without using any custom hardware, and achieves its performance by carefully programming and orchestrating, in software, the interconnects within the Raw chip. Our Raw implementation uses stream-oriented abstractions and differs significantly from that of commercial network processors, which use memory-oriented semantics. Consequently, the Raw router is not only flexible in its architecture and easy to upgrade...

ADAM : a decentralized parallel computer architecture featuring fast thread and data migration and a uniform hardware abstraction

Huang, Andrew S. (Andrew Shane)
Fonte: Massachusetts Institute of Technology Publicador: Massachusetts Institute of Technology
Tipo: Tese de Doutorado Formato: 256 p.; 8574353 bytes; 8574153 bytes; application/pdf; application/pdf
Português
Relevância na Pesquisa
66.13%
The furious pace of Moore's Law is driving computer architecture into a realm where the the speed of light is the dominant factor in system latencies. The number of clock cycles to span a chip are increasing, while the number of bits that can be accessed within a clock cycle is decreasing. Hence, it is becoming more difficult to hide latency. One alternative solution is to reduce latency by migrating threads and data, but the overhead of existing implementations has previously made migration an unserviceable solution so far. I present an architecture, implementation, and mechanisms that reduces the overhead of migration to the point where migration is a viable supplement to other latency hiding mechanisms, such as multithreading. The architecture is abstract, and presents programmers with a simple, uniform fine-grained multithreaded parallel programming model with implicit memory management. In other words, the spatial nature and implementation details (such as the number of processors) of a parallel machine are entirely hidden from the programmer. Compiler writers are encouraged to devise programming languages for the machine that guide a programmer to express their ideas in terms of objects, since objects exhibit an inherent physical locality of data and code. The machine implementation can then leverage this locality to automatically distribute data and threads across the physical machine by using a set of high performance migration mechanisms.; (cont.) An implementation of this architecture could migrate a null thread in 66 cycles - over a factor of 1000 improvement over previous work. Performance also scales well; the time required to move a typical thread is only 4 to 5 times that of a null thread. Data migration performance is similar...

Computer Architecture with Associative Processor Replacing Last Level Cache and SIMD Accelerator

Yavits, Leonid; Morad, Amir; Ginosar, Ran
Fonte: Universidade Cornell Publicador: Universidade Cornell
Tipo: Artigo de Revista Científica
Português
Relevância na Pesquisa
56.13%
This study presents a novel computer architecture where a last level cache and a SIMD accelerator are replaced by an Associative Processor. Associative Processor combines data storage and data processing and provides parallel computational capabilities and data memory at the same time. An analytic performance model of the new computer architecture is introduced. Comparative analysis supported by simulation shows that this novel architecture may outperform a conventional architecture comprising a SIMD coprocessor and a shared last level cache while consuming less power.; Comment: This paper has been withdrawn by the author due to a crucial error in equation 10

Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education

Figueiredo, Renato; Boykin, P. Oscar; Fortes, Jose A. B.; Li, Tao; Peir, Jie-Kwon; Wolinsky, David; John, Lizy; Kaeli, David; Lilja, David; McKee, Sally; Memik, Gokhan; Roy, Alain; Tyson, Gary
Fonte: Universidade Cornell Publicador: Universidade Cornell
Tipo: Artigo de Revista Científica
Publicado em 10/07/2008 Português
Relevância na Pesquisa
56.08%
This paper introduces Archer, a community-based computing resource for computer architecture research and education. The Archer infrastructure integrates virtualization and batch scheduling middleware to deliver high-throughput computing resources aggregated from resources distributed across wide-area networks and owned by different participating entities in a seamless manner. The paper discusses the motivations leading to the design of Archer, describes its core middleware components, and presents an analysis of the functionality and performance of a prototype wide-area deployment running a representative computer architecture simulation workload.; Comment: 11 pages, 2 figures. Describes the Archer project, http://archer-project.org

Pond: A Robust, scalable, massively parallel computer architecture

Spirer, Adam
Fonte: Rochester Instituto de Tecnologia Publicador: Rochester Instituto de Tecnologia
Tipo: Tese de Doutorado
Português
Relevância na Pesquisa
66.15%
A new computer architecture, intended for implementation in late and post silicon technologies, is proposed. The architecture is a fine-grained, inherently parallel system consisting of a large grid of thousands or millions of simple "atomic processors" (APs) employing a simple instruction set. Each AP is configured as either a program instruction or data storage element. These elements are organized into logical entities, analogous to traditional programming functions/methods and data structures. Programming work is underway to compile and run programs from traditional sequential code where parallelism is automatically discovered at the high level on both instruction level and function level, and integrated into the object code that is then sent to the processor. The result is a massively parallel architecture that fully exploits instruction and thread-level parallelism. The architecture design is presented, in-progress work involving conversion of existing code is discussed, and examples are shown to indicate the speedup potential that exists in this new architecture when compared to current architectures.

Design and evaluation of multimedia extensions for the DLX architecture

Hughes, Brian
Fonte: Rochester Instituto de Tecnologia Publicador: Rochester Instituto de Tecnologia
Tipo: Tese de Doutorado
Português
Relevância na Pesquisa
56.08%
Multimedia computer architecture extensions for Hennessy and Patterson's DLX architecture are developed following the study of multimedia applications and existing multimedia architecture extensions. Support for the extensions is added to a VHDL superscalar DLX CPU model as well as a DLX assembler. Key functions used in digital video encoding and decoding are modified to use the extensions, and simulations are undertaken using the VHDL model to determine the speedup offered by the extensions for these functions. The results of the simulations are used to calculate the application speedup based on the function speedup and the fraction of the time that each application spends executing each function. It is shown that the superscalar CPU design limits the performance gain offered by the extensions, and concluded that the effectiveness of the extensions is further limited by the fraction of the application code that can make use of them.

Pond IDE: Machine level program development environment and register transfer level simulator for a massively parallel computer architecture

Muszynski, Jesse
Fonte: Rochester Instituto de Tecnologia Publicador: Rochester Instituto de Tecnologia
Tipo: Tese de Doutorado
Português
Relevância na Pesquisa
66.15%
As computing architectures are being implemented in late and post silicon technologies, fault tolerance and concurrent operation are becoming increasingly important. It is already common knowledge that manufacturers are putting two, four or even more cores on a single silicon die to improve computing performance. The proposed architecture far exceeds this number by grouping thousands or even millions of simple reduced instruction set computing (RISC) processors, each of which is capable of a single operation at a time, and to communicate with its eight nearest neighbors. In this architecture, if a single core or cluster of cores have defects at the time of manufacture, or later in the life of the system, it is possible to test and disable them as necessary. A fine-grained architecture of this kind calls for a parallel programming style. One approach to this problem is the use of a parallelizing compiler. Another approach may be to use one of the several application programming interfaces (APIs) available for standard text based programming languages, with some built-in features for parallel programming. This work has generated a solution for creating machine level parallel programs for the massively parallel computer architecture described above using text and graphical means. To support this programming method...

A coherent sequence of computer architecture laboratory assignments

Patru, Dorin; Oyake, Konboye; Peskin, Eric
Fonte: 9th International Conference on Engineering Education Publicador: 9th International Conference on Engineering Education
Tipo: Proceedings
Português
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66.11%
The Computer Architecture course at the Rochester Institute of Technology (RIT) is taken by undergraduate students in their fourth year of study, after they have had an Introduction to Digital Systems, to Programming in C, and to Microprocessor Programming. The course gives students the computer hardware designer’s perspective, with an emphasis on complete logic design. The objective of the laboratory is the design, simulation and implementation of a processor in a reconfigurable hardware device. Each weekly laboratory assignment builds upon the previous one. The bottom-top design process starts with the design of a combinational logic Arithmetic and Logic Unit, of a Register File and Memory Blocks. The design of the Central Processing Unit is divided into the design of the Data Path and Control Unit. The Instruction Set Architecture is enforced, i.e. the students do not have to come up with their own instruction set. All students must follow general and individual design specifications. The latter are selected using a binary code assigned to each student. The value of each bit chooses between design alternatives such as: Von-Neumann versus Harvard, I/O Mapped versus Memory Mapped Peripherals, 3-bus versus 2-bus architecture, tri-state versus multiplexer data transfer...

Design of a General Purpose 8-bit RISC Processor for Computer Architecture Learning

Hernández Zavala,Antonio; Camacho Nieto,Oscar; Huerta Ruelas,Jorge A.; Carvallo Domínguez,Arodí R.
Fonte: Centro de Investigación en computación, IPN Publicador: Centro de Investigación en computación, IPN
Tipo: Artigo de Revista Científica Formato: text/html
Publicado em 01/06/2015 Português
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66.08%
Computers are becoming indispensable for manipulating most everyday consumer products, ranging from communications and domestic electronics to industrial processes monitoring and control. High performance computer design is not only subject to the technology used for its implementation, it is also a matter of efficient training. The skills that must prevail in a good computer designer come from the type of courses taken and the tools employed during them. This work shows the design of an 8-bit RISC soft-core processor dedicated to a complete understanding of computer architecture. We consider this Processor an effective hands-on training solution for the comprehension of a computer from its lowest level up to testing.