Página 1 dos resultados de 47 itens digitais encontrados em 0.060 segundos

Santos, João Ricardo Borges dos
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## Direct detection and time-locked subsampling applied to pulsed electron paramagnetic resonance imaging

Pursley, Randall H.; Salem, Ghadi; Pohida, Thomas J.; Devasahayam, Nallathamby; Subramanian, Sankaran; Krishna, Murali C.
Tipo: Artigo de Revista Científica
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The application of direct time-locked subsampling (TLSS) to Fourier transform electron paramagnetic resonance (FT-EPR) spectroscopy at radio frequencies (rf) is described. With conventional FT-EPR spectroscopy, the high Larmor frequencies (Lf) often necessitate the use of intermediate frequency (IF) stages to down convert the received free induction decay (FID) signal to a frequency that can be acquired with common data acquisition technology. However, our research focuses on in vivo studies, and consequently utilizes a FT-EPR system with a Lf of 300 MHz. This relatively low frequency Lf, in conjunction with the advent of bandpass sampling analog–to–digital conversion and signal processing technologies, has enabled us to omit the IF stage in our FT-EPR system. With this in mind, TLSS techniques have been developed to directly sample the 300 MHz FID signal at a sampling rate of 80 MHz providing a signal bandwidth of 20 MHz. The required modifications to the data acquisition and processing system specific to this application are described. Custom software developed to control the EPR system setup, acquire the signals, and post process the data, is outlined. Data was acquired applying both coherent averaging and stochastic excitation sequences. The results of these experiments demonstrate digital down conversion of the 300 MHz FID signal to quadrature baseband. Direct FID TLSS eliminates many noise sources common in EPR systems employing traditional analog receiver techniques...

## Ultra-wideband digital baseband; UWB digital baseband

Blázquez-Fernández, Raúl, 1975-
Fonte: Massachusetts Institute of Technology Publicador: Massachusetts Institute of Technology
Tipo: Tese de Doutorado Formato: 152 p.
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The FCC approved the use of Ultra-wideband signals for communication purposes in February 2002 in the band from 3.1GHz to 10.6GHz, effectively opening 7.5GHz of free unlicensed bandwidth. There are two main constraints for the use of this band: a maximum EIRP spectral density of -41.3dBm/MHz and a minimum instantaneous bandwidth of 500MHz. One of the main driving applications of this technology is high data rate communication over short distances. In this thesis two digital baseband receivers for impulse UWB have been designed. The first one was designed for baseband UWB pulses and achieves 193 kbps of wireless communication using impulses of 300 MHz bandwidth and 2% duty cycle, and was part of a system-on-a-chip. The second baseband achieves 100Mbps using impulses of 500 MHz bandwidth in the FCC compliant band, as part of a whole UWB system. Due to its bandwidth the multipath becomes very relevant as the data rate is increased into the range of the hundreds of megabits per second. The current multipath model, used for the development of IEEE standard 802.15.3a is a modified Saleh-Valenzuela model [1] that has a root mean square duration of the impulse response from 5 to 25 ns. The maximum data rate in an UWB system depends on the signal to noise ratio and the multipath.; (cont.) The assessment of the quality of the channel and the exposure of several useful knobs in the baseband to control the complexity of the signal processing implemented allows higher levels of the communication hierarchy to fine-tune the receiver...

## Multitier Wireless Communications

Aazhang, Behnaam; Cavallaro, Joseph R.; Aazhang, Behnaam; Cavallaro, Joseph R.
Tipo: Artigo de Revista Científica
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Journal Paper; Next-generation computing systems will be highly integrated using wireless networking. The Rice Everywhere NEtwork (RENE) project is exploring the integration of WCDMA cellular systems, high speed wireless LANs, and home wireless networks to produce a seamless multitier network interface. We are currently developing a simulation acceleration testbed and a multitier network interface card (mNIC) consisting of DSP processors, custom VLSI ASICs, and FPGAs for baseband signal processing to interact with the various RF units and the host processor. This testbed will also allow us to explore high performance algorithm alternatives through computer aided design tools for rapid prototyping and hardware/software co-design of embedded systems.

## VLSI Architectures for Multitier Wireless Systems

Cavallaro, Joseph R.; Cavallaro, Joseph R.
Tipo: Conference paper
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Conference Paper; Next-generation computing systems will be highly integrated using wireless networking. The Rice Everywhere NEtwork (RENÃ ) project is exploring the integration of WCDMA cellular systems, high speed wireless LANs, and home wireless networks to produce a seamless multitier network interface. We are currently developing a simulation acceleration testbed and a multitier network interface card (mNIC) consisting of DSP processors, custom VLSI ASICs, and FPGAs for baseband signal processing to interact with the various RF units and the host processor. This testbed will also allow us to explore high performance algorithm alternatives through computer aided design tools for rapid prototyping and hardware/software co-design of embedded systems.

## Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers

Rajagopal, Sridhar; Bhashyam, Srikrishna; Cavallaro, Joseph R.; Aazhang, Behnaam; Rajagopal, Sridhar; Bhashyam, Srikrishna; Cavallaro, Joseph R.; Aazhang, Behnaam
Tipo: Conference paper
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Conference Paper; A real-time VLSI architecture is designed for multiuser channel estimation, one of the core base-band processing operations in wireless base-station receivers. Future wireless basestation receivers will need to use sophisticated algorithms to support extremely high data rates and multimedia. Current DSP architectures are unable to fully exploit the parallelism and bit level arithmetic present in these algorithms. These features can be revealed and efficiently implemented by task partitioning the algorithms for a VLSI solution. We modify the channel estimation algorithm for a reduced complexity fixed-point hardware implementation. We show the complexity and hardware required for three different area-time tradeoffs: an area-constrained, a time-constrained and an area-time efficient architecture. The area-constrained architecture achieves low data rates with minimum hardware, which may be used in picocell base-stations. The time-constrained solution exploits the entire available parallelism and determines the maximum theoretical data rates. The area-time efficient architecture meets real-time requirements with minimum area overhead. The orders-of-magnitude difference between area and time constrained solutions reveals significant inherent parallelism in the algorithm. All proposed VLSI solutions exhibit better time performance than a previous DSP implementation.

## DSP architectural considerations for optimal baseband processing

Rajagopal, Sridhar; Rixner, Scott; Cavallaro, Joseph R.; Aazhang, Behnaam; Rajagopal, Sridhar; Rixner, Scott; Cavallaro, Joseph R.; Aazhang, Behnaam
Tipo: Conferência ou Objeto de Conferência
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Presentation; The data rate requirements for future wireless systems has increased by orders-of-magnitude (from Kbps to several Mbps), requiring more sophisticated algorithms for their implementation. This tutorial will explore different architectural issues to consider for optimal wireless baseband processing. It will look at research into real-time architectural design issues such as number of functional units, data access from memory and sequential traceback for Viterbi decoding using digital signal processors

## Hardware/Software Co-design Methodology and DSP/FPGA Partitioning: A Case Study for Meeting Real-Time Processing Deadlines in 3.5G Mobile Receivers

Brogioli, Michael; Radosavljevic, Predrag; Cavallaro, Joseph R.
Tipo: Conference paper
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This paper presents a DSP/FPGA hardware/software partitioning methodology for signal processing workloads. The example workload is the channel equalization and user-detection in HSDPA wireless standard for 3.5G mobile handsets. Channel equalization and user-detection is a major component of receiver baseband processing and requires strict adherence to real time deadlines. By intelligently exploring the embedded design space, this paper presents a hardware/software system-on-chip partitionings that utilizes both DSP and FPGA based coprocessors to meet and exceed the real time data rates determined by the HSDPA standard. Hardware and software partitioning strategies are discussed with respect to real time processing deadlines, while an SOC simulation toolset is presented as vehicle for prototyping embedded architectures.

## Multitier Wireless Systems

Aazhang, Behnaam; Cavallaro, Joseph R.
Fonte: Aalborg University, Denmark Publicador: Aalborg University, Denmark
Tipo: Conference paper
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Next-generation computing systems will be highly integrated using wireless networking. The Rice Everywhere NEtwork (RENE) project is exploring the integration of WCDMA cellular systems, high speed wireless LANs, and home wireless networks to produce a seamless multitier network interface. We are currently developing a simulation acceleration testbed and multitier network interface card (mNIC) consisting of DSP processors, custom VLSI ASICs, and FPGAs for baseband signal processing to interact with the various RF units and the host processor. This testbed will also allow us to explore high performance algorithm alternatives through computer aided design tools for rapid prototyping and hardware/software co-design of embedded systems.

## MIMO OTA testing based on transmit signal processing

Gutiérrez Terán, Jesús; Ibáñez Díaz, Jesús María; Pérez Arriaga, Jesús
Fonte: Hindawi Publishing Corporation Publicador: Hindawi Publishing Corporation
Tipo: info:eu-repo/semantics/article; publishedVersion
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Usually, multiple-input-multiple-output (MIMO) testbeds are combined with channel emulators for testing devices and algorithms under controlled channel conditions. In this work, we propose a simple methodology that allows over-the-air (OTA) MIMO testing using a MIMO testbed solely, avoiding the use of channel emulators. The MIMO channel is emulated by linearly combining the signals at the testbed transmitter. The method is fully flexible, so it is able to emulate any equivalent baseband narrowband MIMO channel by adequately selecting the weights of the linear combination. We derive closed-form expressions for the computation of such weights. To prove its feasibility, the method has been implemented and tested over a commercial MIMO testbed.

## Analog-to-digital signal processing in a prototype SATCOM signal analyzer

Ohlson, John Everett; Zell, William B.
Tipo: Relatório Formato: 103 p. : ill. ; 28 cm.
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A prototype SATCOM Signal Analyzer (SSA) has been designed which performs spectral analysis on transponder signals from the Navy's UHF communications satellites. As an integral part of the SSA, the Analog to Digital Control and Conversion subsystem converts four channels of baseband analog signals into equivalent digital representations while operating at variable sampling rates and offering either twelve or eight bits of resolution of the analog signal. The digital data thus derived is presented to an array processor for Fast Fourier Transform processing. This report documents the design and construction of the Analog to Digital Control and Conversion subsystem.; Prepared for: Naval Electronic Systems Command PME-106-1, Washington, D.C. 20360 -- Cover.; http://archive.org/details/analogtodigitals00ohls; N0003980WR09137; NA

## Group Sparse Beamforming for Green Cloud-RAN

Shi, Yuanming; Zhang, Jun; Letaief, Khaled B.
Tipo: Artigo de Revista Científica
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A cloud radio access network (Cloud-RAN) is a network architecture that holds the promise of meeting the explosive growth of mobile data traffic. In this architecture, all the baseband signal processing is shifted to a single baseband unit (BBU) pool, which enables efficient resource allocation and interference management. Meanwhile, conventional powerful base stations can be replaced by low-cost low-power remote radio heads (RRHs), producing a green and low-cost infrastructure. However, as all the RRHs need to be connected to the BBU pool through optical transport links, the transport network power consumption becomes significant. In this paper, we propose a new framework to design a green Cloud-RAN, which is formulated as a joint RRH selection and power minimization beamforming problem. To efficiently solve this problem, we first propose a greedy selection algorithm, which is shown to provide near- optimal performance. To further reduce the complexity, a novel group sparse beamforming method is proposed by inducing the group-sparsity of beamformers using the weighted $\ell_1/\ell_2$-norm minimization, where the group sparsity pattern indicates those RRHs that can be switched off. Simulation results will show that the proposed algorithms significantly reduce the network power consumption and demonstrate the importance of considering the transport link power consumption.

## Dynamic Nested Clustering for Parallel PHY-Layer Processing in Cloud-RANs

Fan, Congmin; Zhang, Ying Jun; Yuan, Xiaojun
Tipo: Artigo de Revista Científica
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Featured by centralized processing and cloud based infrastructure, Cloud Radio Access Network (C-RAN) is a promising solution to achieve an unprecedented system capacity in future wireless cellular networks. The huge capacity gain mainly comes from the centralized and coordinated signal processing at the cloud server. However, full-scale coordination in a large-scale C-RAN requires the processing of very large channel matrices, leading to high computational complexity and channel estimation overhead. To resolve this challenge, we exploit the near-sparsity of large C-RAN channel matrices, and derive a unified theoretical framework for clustering and parallel processing. Based on the framework, we propose a dynamic nested clustering (DNC) algorithm that not only greatly improves the system scalability in terms of baseband-processing and channel-estimation complexity, but also is amenable to various parallel processing strategies for different data center architectures. With the proposed algorithm, we show that the computation time for the optimal linear detector is greatly reduced from $O(N^3)$ to no higher than $O(N^{\frac{42}{23}})$, where $N$ is the number of RRHs in C-RAN.

## A software baseband receiver for pulsar astronomy at GMRT

Joshi, Bhal Chandra; Ramakrishna, Sunil
Tipo: Artigo de Revista Científica
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A variety of pulsar studies, ranging from high precision astrometry to tests for theories of gravity, require high time resolution data. Few such observations at more than two frequencies below 1 GHz are available. Giant Meterwave Radio Telescope (GMRT) has the unique capability to provide such multi-frequency pulsar data at low observation frequencies, but the quality and time resolution of pulsar radio signals is degraded due to dispersion in the inter-stellar medium at these frequencies. Such degradation is usually taken care of by employing specialized digital hardware, which implement coherent dedispersion algorithm. In recent years, a new alternative is provided by the availability of cheap computer hardware. In this approach, the required signal processing is implemented in software using commercially off-the-shelf available computing hardware. This makes such a receiver flexible and upgradeable unlike a hardware implementation. The salient features and the modes of operation of a high time resolution pulsar instrument for GMRT based on this approach is described in this paper. The capability of the instrument is demonstrated by illustrations of test observations. We have obtained the average profile of PSR B1937+21 at 235 MHz for the first time and this profile indicates a scattering timescale of about 300 us. Lastly...

## Improving Latency in a Signal Processing System on the Epiphany Architecture

Brauer, Peter; Lundqvist, Martin; Mällo, Aare
Tipo: Artigo de Revista Científica
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In this paper we use the Adapteva Epiphany manycore chip to demonstrate how the throughput and the latency of a baseband signal processing chain, typically found in LTE or WiFi, can be optimized by a combination of task- and data parallelization, and data pipelining. The parallelization and data pipelining are facilitated by the shared memory architecture of the Epiphany, and the fact that a processor on one core can write directly into the memory of any other core on the chip.; Comment: Draft paper submitted to and accepted by PDP 2016, 24th Euromicro International Conference on Parallel, Distributed and Network-Based Processing. Heraklion Crete, Greece, 17th-19th February 2016

## Digital Signal Processing using Stream High Performance Computing: A 512-input Broadband Correlator for Radio Astronomy

Kocz, J.; Greenhill, L. J; Barsdell, B. R.; Price, D.; Bernardi, G.; Bourke, S.; Clark, M. A.; Craig, J.; Dexter, M.; Dowell, J.; Eftekhari, T.; Ellingson, S.; Hallinan, G.; Hartman, J.; Jameson, A.; MacMahon, D.; Taylor, G.; Schinzel, F.; Werthimer, D.
Tipo: Artigo de Revista Científica
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A "large-N" correlator that makes use of Field Programmable Gate Arrays and Graphics Processing Units has been deployed as the digital signal processing system for the Long Wavelength Array station at Owens Valley Radio Observatory (LWA-OV), to enable the Large Aperture Experiment to Detect the Dark Ages (LEDA). The system samples a ~100MHz baseband and processes signals from 512 antennas (256 dual polarization) over a ~58MHz instantaneous sub-band, achieving 16.8Tops/s and 0.236 Tbit/s throughput in a 9kW envelope and single rack footprint. The output data rate is 260MB/s for 9 second time averaging of cross-power and 1 second averaging of total-power data. At deployment, the LWA-OV correlator was the largest in production in terms of N and is the third largest in terms of complex multiply accumulations, after the Very Large Array and Atacama Large Millimeter Array. The correlator's comparatively fast development time and low cost establish a practical foundation for the scalability of a modular, heterogeneous, computing architecture.; Comment: 10 pages, 8 figures, submitted to JAI

## Distributed Fronthaul Compression and Joint Signal Recovery in Cloud-RAN

Rao, Xiongbin; Lau, Vincent K. N.
Tipo: Artigo de Revista Científica
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The cloud radio access network (C-RAN) is a promising network architecture for future mobile communications, and one practical hurdle for its large scale implementation is the stringent requirement of high capacity and low latency fronthaul connecting the distributed remote radio heads (RRH) to the centralized baseband pools (BBUs) in the C-RAN. To improve the scalability of C-RAN networks, it is very important to take the fronthaul loading into consideration in the signal detection, and it is very desirable to reduce the fronthaul loading in C-RAN systems. In this paper, we consider uplink C-RAN systems and we propose a distributed fronthaul compression scheme at the distributed RRHs and a joint recovery algorithm at the BBUs by deploying the techniques of distributed compressive sensing (CS). Different from conventional distributed CS, the CS problem in C-RAN system needs to incorporate the underlying effect of multi-access fading for the end-to-end recovery of the transmitted signals from the users. We analyze the performance of the proposed end-to-end signal recovery algorithm and we show that the aggregate measurement matrix in C-RAN systems, which contains both the distributed fronthaul compression and multiaccess fading, can still satisfy the restricted isometry property with high probability. Based on these results...

## Efficient Test Methods for RF Transceivers

Erdogan, Erdem Serkan
Tipo: Dissertação Formato: 8339500 bytes; application/pdf
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Advancements of the semiconductor technology opened a new era in

wireless communications which led manufacturers to produce faster,

more functional devices in much smaller sizes. However, testing

these devices of today's technology became much harder and expensive

due to the complexity of the devices and the high operating speeds.

Moreover, testing these devices becomes more important since decreasing

feature sizes increase the probability of parametric and catastrophic

faults because of the severe effects of process variations. Manufacturers

have to increase their test budgets to address quality and reliability

concerns. In the radio frequency (RF) domain, overall test cost are higher

due to equipment costs, test development and test time costs. Advanced

circuit integration, which integrates various analog and digital circuit

blocks into single device, increases test costs further because of the

additional tests requiring new test setups with extra test equipments.

Today's RF transceiver circuits contain many analog and digital circuit

blocks...

## A Digital signal processing-based predistortion technique for reduction of intermodulation distortion

Buckley, Richard James
Fonte: Rochester Instituto de Tecnologia Publicador: Rochester Instituto de Tecnologia
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Linearization of power amplifiers has been the topic of many studies, dating back to the work of H. S. Black in the 1920s. For many applications, the well-documented techniques of feedforward and feedback can be used to design low intermodulation distortion (IMD) amplifiers. However, certain applications, including the design of high-power, radio frequency amplifiers, preclude the use of these techniques. The work herein describes an alternative to presently accepted distortion reduction techniques. In-band IM distortion (multi-tone distortion located close in frequency to the desired signal) , is reduced by modifying a baseband input, upconverting this signal to the transmission frequency, then performing the amplification. This allows DSP hardware to be used, resulting in a novel IMD reduction method. The approach presented is unique in that multiple orders of nonlinearity are reduced using DSP technology, at baseband, through a commonly used method of upconversion. Existing work has addressed mostly third-order, analog solutions applied at the frequency of transmission. Theoretical work, simulations, and experimental results are used to describe the technique. Advantages and limitations are discussed, as are areas for future work.

## Design of a 14-bit fully differential discrete time delta-sigma modulator

Nathany, Sumit Kumar
Fonte: Rochester Instituto de Tecnologia Publicador: Rochester Instituto de Tecnologia
Tipo: Tese de Doutorado Formato: 2242095 bytes; application/pdf
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Analog to digital converters play an essential role in modern mixed signal circuit design. Conventional Nyquist-rate converters require analog components that are precise and highly immune to noise and interference. In contrast, oversampling converters can be implemented using simple and high-tolerance analog components. Moreover, sampling at high frequency eliminates the need for abrupt cutoffs in the analog anti-aliasing filters. A noise shaping technique is also used in DS converters in addition to oversampling to achieve a high resolution conversion. A significant advantage of the method is that analog signals are converted using simple and high-tolerance analog circuits, usually a 1-bit comparator, and analog signal processing circuits having a precision that is usually much less than the resolution of the overall converter. In this thesis, a technique to design the discrete time DS converters for 25 kHz baseband signal bandwidth will be described. The noise shaping is achieved using a switched capacitor low-pass integrator around the 1-bit quantizer loop. A latched-type comparator is used as the quantizer of the DS converter. A second order DS modulator is implemented in a TSMC 0.35 Âµm CMOS technology using a 3.3 V power supply. The peak signal-to-noise ratio (SNR) simulated is 87 dB; the SNDR simulated is 82 dB which corresponds to a resolution of 14 bits. The total static power dissipation is 6.6 mW.